1. Field of the Invention
The present invention relates to a signal processor suitably used as a sound generator of electronic musical instruments.
2. Description of the Related Art
A signal processor including a logic operation element which is called a digital signal processor (DSP) and processes multiplication-addition-calculation (MAC); product-sum-operation) at high speed under the control by the CPU has been known. In general, in the signal processor, data to be processed is stored in an external memory. According to a direction by the CPU, the data to be processed is sequentially captured from the external memory and provided with signal processing. For example, in a signal processor used as a sound generator of electronic musical instruments, waveform data stored in the external memory is read for each sampling period, the read waveform data is provided with delay feedback operation and filter operation (for example, FIR filter) to form musical sound with various overtone structures, the formed musical sound is provided with various effects such as delay, and the result is outputted.
As such a signal processor as above, for example, Japanese Laid-Open Patent Publication No. 10-260831 discloses a signal processor as follows. The signal processor is composed of a first processing section for performing signal processing under the control by the CPU and a second processing section for performing read/write processing in relation to the external memory independently of the first processing section. The first processing section performs the signal processing in preference to the read/write processing of the second processing section which synchronizes a time slot different from the time slot of the first processing section. Thereby, the external memory including the second processing section functions as an internal memory for the first processing memory. In result, wasteful time in accessing the external memory is omitted, and the processing speed is improved.
In a signal processor structured so that the CPU and the DSP share an external memory via the same bus, the CPU manages the bus fundamentally. In the signal processor structured as above, when the DSP occupies the bus, the DSP requests the CPU to release the bus, and the CPU correspondingly releases the bus. Therefore, the CPU receiving the bus release request needs latency variable to some extent from receiving the request from the DSP to actually releasing the bus. Further, the DSP side needs to wait until the request is received by the CPU every time when the DSP requests the CPU for memory access. Therefore, there is a problem that it causes lowering of the processing efficiency of the processor as a whole.